PCB basics for mechanical engineers

Breadboards work for prototypes. Production robots have custom PCBs — they're more reliable, smaller, cheaper at scale. Spinning your first PCB sounds intimidating; it's a half-day learning curve in 2026 thanks to KiCad and JLCPCB. Here's the working knowledge to get a usable board manufactured for ~$5.

The KiCad workflow

KiCad is the open-source PCB tool. Free, capable, used by serious hardware companies in 2026. The five steps:

1. Schematic capture: draw the circuit. Components, wires, labels.
2. PCB layout: place footprints; route copper traces.
3. Design rule check (DRC): verify minimum trace widths, clearances.
4. Generate Gerber files: industry-standard manufacturing format.
5. Order from a fab (JLCPCB, OSHPark, PCBWay).

Steps 1–3: a few hours for a small board. Step 4: a few clicks. Step 5: $2–10 + shipping; the board arrives in 1–2 weeks.

Schematic capture

Components from libraries (KiCad ships thousands; SnapEDA / Octopart provide more). Wire pins together. Add labels for nets. Label power rails (VCC, GND).

Discipline that matters:

• Decoupling caps near every IC: 0.1 µF ceramic; place schematically near the IC's VCC/GND.
• Pull-ups / pull-downs explicit: don't rely on internal pulls.
• Test points: a few pads for oscilloscope probes when debugging.
• Power input filtering: bulk cap at the connector input.
• Mounting holes: 4 corners, M3 size standard.

PCB layout

Convert schematic to layout (KiCad's "Update PCB from Schematic"). Components appear with rats-nest lines connecting them.

Key choices:

• Number of layers: 2-layer is cheapest ($2–5 at JLCPCB). 4-layer ($30+) is dense designs.
• Board size: smaller is cheaper. 100 mm × 100 mm is the breakpoint at most fabs.
• Component placement: ICs near their decoupling caps; connectors at the edges; mechanical features (mounting holes, cutouts) per chassis.
• Trace width: 0.25 mm minimum (cheap fabs); 0.15 mm if you need density. Power traces wider — 0.5 mm for 1A, 1 mm for 5A.
• Trace clearance: 0.15 mm minimum.

The 2-layer routing pattern

Top layer for signals; bottom layer is mostly ground plane. Drop vias to ground anywhere ground is needed. Signals jump to bottom only when needed (a "horizontal" signal can stay on top, "vertical" on bottom — the classical convention).

The ground plane provides:

• Low-impedance return path for currents.
• Shielding between top-layer signals.
• Heat sink for power components.

Don't break the ground plane unnecessarily. Sliced grounds re-introduce ground loops.

The components most boards need

• USB-C connector: hot-swap robots; programming via UART.
• 3.3V LDO (AMS1117 or similar): drops 5V to 3.3V for the MCU.
• Reset button: every MCU should be resettable.
• Indicator LEDs: power, status; cheap visibility.
• Header pins: 2.54 mm pitch for connecting to peripherals.
• SWD / programming connector: for STM32 it's a 4-pin header (SWDIO, SWCLK, RST, GND).

SMT vs through-hole

Through-hole (TH) components are hand-solderable but bigger; surface-mount (SMT) is smaller but needs a hot-air station or reflow oven.

For first PCBs:

• Use TH for connectors and large caps (you can solder them by hand).
• Use 0805 SMT for resistors and small caps (manageable with a soldering iron + tweezers).
• Avoid 0402 and smaller until you have practice.

JLCPCB's PCBA service: they assemble SMT parts for you (~$30–80 setup + parts). Worth it for boards with many small components.

The design rule check (DRC)

Before exporting Gerbers, run DRC. KiCad highlights:

• Trace too narrow.
• Trace too close to another.
• Pads too small for the drill.
• Disconnected nets.
• Components overlapping.

Don't ignore DRC errors. They translate directly to manufacturing failures.

The Gerber export

"Plot" → select all layers → output to a folder. Zip the resulting files. Upload to JLCPCB.

Standard layers in the zip:

• F.Cu, B.Cu (top, bottom copper).
• F.Mask, B.Mask (solder mask).
• F.Silk, B.Silk (silkscreen labels).
• Edge.Cuts (board outline).
• NPTH, PTH drill files.

Ordering from JLCPCB

Upload Gerbers; review the visual; pick options:

• Quantity: 5 minimum; 10 isn't much more.
• Layers: 2 (cheapest), 4, 6, 8.
• Thickness: 1.6 mm standard.
• Color: green is cheapest; black or blue add a few dollars.
• Surface finish: HASL is cheapest; ENIG (gold-plated) is required for very fine pitch.

5 boards of a 50 × 50 mm 2-layer board: ~$5 + shipping. Place the order; boards arrive in ~10 days.

The first-time gotchas

• Wrong footprint: ordered the part but the schematic footprint doesn't match. Always cross-check datasheet pinout.
• Pin 1 marker missing: orientation ambiguous; soldered backward. Add silkscreen pin-1 dots.
• Vias too close to pads: solder bridges. Maintain 0.3 mm minimum.
• Forgot mounting holes: how does this board attach to anything?
• Power trace too narrow: melts under load. Calculate using IPC-2152.
• USB-C cable orientation: USB-C has 24 pins; you need to wire CC1/CC2 with 5.1 kΩ resistors for power negotiation.

The 50-line minimum board

For your first PCB: an ESP32-S3 breakout with USB-C, 3.3V LDO, reset button, status LED, and 30 GPIO header pins. Two-layer, 50 × 30 mm. Cost: ~$5 for 5 boards.

This is the "hello world" of PCB design. Once you've spun it and hand-soldered the parts, you can spin anything.

The 2026 reality

For hobby robotics, the breadboard-to-PCB transition is the moment your robot looks "real." A 2-layer custom board with proper connectors and screws looks 10× more polished than the same circuit on a breadboard. And it actually works reliably.

Plan for v1 to have bugs (a wire jumper here, a missing component there). v2 is where it gets clean. Both costs are still under $20.

Exercise

Pick a small project (an ESP32 breakout, a motor-driver carrier). Design it in KiCad over an afternoon. Run DRC. Export Gerbers. Order from JLCPCB. When the boards arrive in two weeks, hand-solder one. The first time your custom board boots and runs your firmware is the moment "embedded engineer" becomes a real thing you can do.

Next

Thermal design — keeping the components from cooking themselves under load.